NXP (previously PLSense) Testimonials

The PLS15 chip was a unique chip that operates on programmable voltage from the Sub Threshold domain to the nominal voltage domain which is optimized on the fly to fit the performance of the chip and the environmental conditions. The PLS15 was manufacture at the 40nm ULP TSMC process.

AAI was responsible for the Physical Design of this project which was very complex and includes different voltage domains, complex power down modes and complex UPF. The project also includes a special Sub Threshold standard cell library and special low power Analog block which needed to be used at the P&R and the SoC integration. AAI did all the Physical design work and integration of this chip until ready GDS that was delivered to the Fab.

AAI did a very good and professional work, helping the PLSense team to solve different issue which relates to the PLSense special standard cell libraries and Analog blocks. The AAI team was very dedicated and pushed the work forward in order to release the Tape-Out on time.

AAI also did for us the RTL to GDSII of the PL10TC project, which was an earlier version of the PLS15. Staying with AAI to work also on the PLS15 device, demonstrates our satisfaction and appreciation of AAI work.

Best Regards,

Uzi Zangi

CEO of the ex-PLSense operation