ASIC Design & Manufacturing
30 years, 350 Tapeouts
30 years, 350 Tapeouts
We'll check current technological solutions of the different foundries and verify that their future plans meet your project's targets.
We'll evaluate packaging options with assembly houses and present the best alternatives.
We'll appraise your test requirements and find the best platform and vendor for test.
We'll assist in choosing the best vendor for your reliability and qualification.
RTF Logic Design
IP Integration
Synthesis
Formal Proof
DFT Insertion
ATPG
Place & Route
Timing Closure
Signal Integrity
Extract \ DRC \ LVS
Tape-out
GDSII Generation
Productization
Wafer Fabrication
Package Design
Test Development
Qualification
Reliability
Assembly & Test
Yield Optimization
Failure Anlysis
Logistics
Analog Design:
A/D D/A Converters
PLLs & CDRs
Change Pumps
Regulated Power
Line Drivers
Electro Optical Drivers
FPGA Design
Structured ASIC
Design
Deep-sub-micron (0.18u, 0.13u, 90nm, 65nm, 40nm, 28nm) System-on-Chip
System architecture in CPU environment (ARM, MIPS, ARC)
Mixed Signal and Full Custom analog designs
IP integration and verification (ARM, MIPS, USB2/3, PCI-Ex, DDR2/3, etc.)
Design for test and automatic test pattern generation (ATPG)
Design methodologies for low power applications
Design for manufacturability (DFM): yields, quality, reliability
Advanced assembly techniques: CSP, Flip-Chip, BGA, MCP/SIP
Test program and test hardware development and debug
Our design platform is based on Synosys tools for RTL to GDSII flow and full custom analog design.
Our design team is well experienced with other advanced CAD tools, e.g. Cadence and Mentor.
Our Design Partners:
Utilizing our in-depth industry knowledge and strong links with world-class semiconductor vendors, we grant our customers access to the most advanced design and manufacturing technologies, while providing more flexibility during the critical decision making process.
AAI maintains a strong in-house team with a wide variety of specialized skills in ASIC/SoC, analog and FPGA design; product engineering and production handling. Our team will help you not only to design the chip, but to find the best vendors for your project and to arrange a smooth tape-out and corner lot characterization. We'll develop for you the most attractive packaging solution and most efficient test program. Our team is dedicated to providing you with timely deliveries of superior quality products.
AAI offers a full range of quality solutions for the entire product life span. Yield optimization services include yield analysis, corner lot characterization, and process re-targeting. Complete support for new products is provided, including new product qualification, failure analysis, DPPM optimization and supplier change notification programs.